The present invention relates to dual-port static random access memory (SRAM) cells. More particularly, the invention relates to dual-port SRAM cells having mono-bit line operation on each port and inverters coupled to local pseudo-ground lines.
Dual Port SRAMs ("DPSRAMs") find widespread use in the electronics industry. Conventional DPSRAMs employ either an 8-transistor cell or a 6-transistor cell. Each has its own advantages and disadvantages. Generally, 6-transistor cells are compact but they operate more slowly. The 8-transistor cells operate faster (they are true dual port cells employing a separate word line for each port), but they occupy more space.
Conventional 6-transistor DPSRAMs require only four N channel transistors, two P channel transistors, and two metal bit lines running on top of the cell. A conventional 6-transistor DPSRAM is illustrated in FIG. 1. It operates as follows.
In standby mode, an SRAM cell 2 statically holds a bit value on two cross-coupled CMOS inverters 4 and 6. The output of inverter 4 feeds the input of inverter 6 and the output of inverter 6 feeds the input of inverter 4. Thus, a first logical bit value is held on the left side of cell 2 and the complementary value is held on the right side of the cell. During standby ode, no information is being read from or written cell 2. Thus, access to the cell is blocked. This is accomplished by holding two NMOS access transistors 8 and 10 in a non-conductive state. One source/drain diffusion of transistor 8 is connected to the left port of cell 2 and one source/drain diffusion of transistor 10 is connected to the right port of cell 2. The other source/drain diffusion transistor 8 is connected to a bit line 14 and the other source/drain diffusion of transistor 10 is connected to a bit line 16. In addition, a word line 12 is connected to the gates of both access transistors 8 and 10 and thereby controls the gate potential of both of these transistors. During standby mode, the potential on a word line 12 is held below the threshold voltage of NMOS transistors 8 and 10.
During read mode, bit lines 14 and 16 are initially precharged to an intermediate potential such as Vdd/2, for example. Then, access transistors 8 and 10 are switched on by applying a potential above the threshold voltage to word line 12. At that point, the voltage on the bit lines changes to reflect the value stored on cross-coupled inverters 4 and 6. Assume, for example, that the left side of the cross-coupled inverters has a "high" value ("1") and the right side has a "low" value ("0"). In that case, when access transistors 8 and 10 are turned on, the potential on bit line 16 drops from Vdd/2 to approximately 0. Concurrently, the potential on bit line 14 increases from Vdd/2 to a higher value. That higher value is not quite Vdd ("1"). Rather, because of the body effect associated with NMOS transistor 8, the potential on bit line 14 increases to at most Vdd-Vt. Vt is the threshold voltage of NMOS transistor 8.
While word line 1 is set of Vdd (or other value over the threshold voltage of the NMOS transistors), a sense amplifier detects and compares the voltages on bit lines 14 and 16. From this comparison, it can determine what value is stored on cell 2.
During the write operation, bit lines 14 and 16 are set at complementary voltages. For example, if bit line 14 is set to a high voltage, bit line 16 is set to a low voltage, or vice versa. Assuming for the moment that the cell is storing the low value on the left side and a high value on the right side and that a new value is to be written in which the low value is on the left side and the high value is on the right side, than a low value (0) is applied to bit line 14 and a high value (Vdd) is applied to bit line 16. Then, word line 12 is set to Vdd so that access transistors 8 and 10 are switched on. On the left side of cell 2, the 0 is transferred to the cross-coupled inverters essentially at the level of 0. On the right side, however, the value of Vdd (high) is not transferred at that level. Rather, the transfer potential will at most be Vdd-Vt because of the body effect as explained above.
Because the system is attempting to switch the state of the cross-coupled inverters 4 and 6, a conflict arises, at least temporarily, within cell 2. Specifically, because the output of inverter 4 is held at 0, it is difficult to switch the value on the right side of the cell to Vdd, especially given that the level transferred from bit line 16 is only Vdd-Vt. The problem is compounded because of the high static noise margins employed to keep the values on SRAM cells stable. Because of these effects, it is virtually impossible to switch the state of the right side of cross-coupled inverters 4 and 6 from low to high by simply applying a high value to bit line 16. The solution is to force a 0 (low) on the other side of the memory cell. As two complementary values (high and low) are written into the cell, two complementary bit lines are necessary to make the operations possible. To effect the transition, bit lines 16 and 14 must "push and pull" at the same time.
In this 6-transistor cell, it is impossible to use two ports at the same time as they share a word line and bit lines. That is, both bit lines and the word line must participate in any read or write operation. Thus, the ports must be selected one after the other, thereby reducing the available speed by a factor of 2. Further such access requires peripheral arbitration logic in order to handle the different selections. Such extra logic complicates the device design.
A standard 8-transistor DPSRAM cell 21 is depicted in FIG. 2. Such cells are commonly used in FIFOs and other applications. Cell 21 includes cross-coupled inverters 23 and 25 arranged in the same manner as inverters 4 and 6 in cell 2. This cell includes two "true" ports. A first port is controlled by a word line 27 in conjunction with bit lines 29 and 31. Word line 27 controls the gates of two NMOS access transistors 33 and 35. A second port is controlled by a word line 37 and bit lines 39 and 41. Word line 37 controls the potential on the gates of two NMOS access transistors 43 and 45. As shown, access transistors 33 and 35 of the first port are arranged at opposite sides of cell 21 and NMOS access transistors 43 and 45 of the second port are also arranged at opposite sides of the cell.
In operation, cell 21 acts much like cell 2, except that because it is controlled by two "true" ports, each with its own compliment of a word line, two bit lines, and two access transistors, it can be accessed through each port nearly simultaneously. In stand-by mode, word lines 27 and 37 are held at a low level. During read or write through the first port, word line 27 is set to a high level (e.g., Vdd). During a read operation through the first port, bit lines 29 and 31 are precharged to Vdd/2 and then, after word line 27 is set high, their outputs are ready by an SRAM sensing circuit and compared. During a write operation, cross-coupled inverters 23 and 25 are pushed and pulled simultaneously by applying complementary values on bit lines 29 and 31 while word line 27 is held high. The second port operates in essentially the same manner. During read, bit lines 39 and 41 are precharged to Vdd/2. Then, when word line 37 is set high, the values on word lines 39 and 41 (now affected by the internal value stored on the cross-coupled inverters) are compared by a sensing circuit. Finally, during the write operation through the second port, complementary values are applied to bit lines 39 and 41 while word line 37 is set high.
While this 8-transistor cell has found wide application, its major problem is the large are that it occupies. It requires six N channel transistors, two P channel transistors, and four metal bit lines running on top of the cell.
Other multiport cells have the same issues. In fact, they can be even more difficult to implement because, in general, the static noise margin is intentionally increased to compensate for the effects of additional access modes. So large cell size becomes the only known option.
For the above reasons an improved high density SRAM is needed.